How I can parallelize a RAM in FPGAhttps://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco

ep#22-Multiplier optimization

May 13th, 2019 5m 23s

Learn how to optimize a multiplier in particular cases:For a technical analysis go to the post:https://surf-vhdl.link/OptimizationVhdl12b25Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhd

Ep#21-Serial-to-Parallel Parallel-to-Serial converter

Apr 28th, 2019 7m 24s

Link to the post:https://surf-vhdl.link/99990Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesM

Q&A#09-I need a clock!

Apr 23rd, 2019 9m 1s

In this podcast we will understand how to connect a clock signal to our FPGAWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courses

Q&A#08- What is the dithering

Apr 10th, 2019 4m 30s

What is dithering? Where we can use this technique?Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/co

ep#20-VHDL Generic

Apr 6th, 2019 5m 34s

VHDL GenericWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://w

Ep#19-Iterative statement

Mar 22nd, 2019 4m 43s

Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use thishttps://t.me/SurfVhdl/92Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: p

Ep#18-the conditional assignment in VHDL

Mar 18th, 2019 7m 28s

Let’s understand how to implement a conditional statement in VHDLimage for the episodehttp://t.me/SurfVhdl/86Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/fr

ep#17-wait

Mar 13th, 2019 5m 22s

Wait Statements in VHDLReference to pictures:https://t.me/SurfVhdl/82Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps:/

Q&A#07- What is the first thing that a recruiter does?

Mar 7th, 2019 4m 4s

Q&A#07- What is the first thing that a recruiter does?When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?What can you do in order to result a VHDL user?Let’s see i

Ep#16-VHDL process

Mar 6th, 2019 7m 17s

And now is time to introduce formally a Processlink to the imageshttps://t.me/SurfVhdl/78Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeac

Q&A#06- How can I generate a new clock from a reference clock?

Mar 1st, 2019 10m 38s

I receiver a question from Sandip. He got my reference, from my post on DDS.The question is:“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.Is it possible

Ep#15-VHDL Packages

Feb 14th, 2019 3m 51s

VHDL Packageshttp://t.me/SurfVhdl/74Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by F

Ep#14-VHDL object

Feb 11th, 2019 6m 11s

After signal introduction, let's view what are the remaining VHDL objectsImages https://t.me/SurfVhdl/72Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/frances

Q&A#05- Does the USB transfer work as UART?

Feb 10th, 2019 9m 15s

I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC. Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB i

QA#04-What is the VHDL design flow

Feb 8th, 2019 7m 9s

In this Q&A episode I want to answer to the question on what is the VHLD design flowTo better follow the episode, see the picture on the telegram channelhttps://t.me/SurfVhdl/65Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYo

Ep#13-a way to remember-the flip-flop

Feb 7th, 2019 5m 41s

Introducing Flip-Flop in VHDLLink to the picture in the telegram channelhttps://t.me/SurfVhdl/61Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfv

QA#3-plzz send the test bench

Feb 5th, 2019 3m 40s

This is the question many of you ask me very oftenI wish to give you some hint and a test bench template I use in my VHDL designs Here the link to the test bench template: https://t.me/SurfVhdl/58Websitehttps://surf-vhdl.comTelegram channelht

Ep#12-VHDL Simulation

Feb 3rd, 2019 5m 51s

A brief overview to setup a ModelSim simulation environmentLink to the episode#12 picturet.me/SurfVhdl/53Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/france

Ep#11-what is a signal

Feb 1st, 2019 3m 53s

Introduce signal in VHDL, what is a signal and how to use it.Image relative to this episodeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTe

Ep#10-More on driver the resolution function

Jan 30th, 2019 8m 13s

Solving a dispute in VHDL: the resolution functionLink to image for the episode#10Solving a dispute in VHDL: the resolution functiont.me/SurfVhdl/50Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast

Ep#09-What is a driver in VHDL

Jan 29th, 2019 3m 57s

What is a driver in VHDL?Images for the episodet.me/SurfVhdl/46Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-

QA#2-SPI-controller-simulation with Vivado

Jan 28th, 2019 2m 3s

In this brief episode I want to answer a question from Klajdi on simulation of SPI controller using Vivado Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/fran

QA#1-Do we need clock and address

Jan 26th, 2019 3m 55s

Answering to Prashant. He asked me this question “What do we have to give as an input for i_clk and i_addr?”relative to the post: https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/Websitehttps://surf-vhdl.comTelegram channelhttps://t.m

Ep#08-concurrency

Jan 25th, 2019 6m 36s

In this episode we will introduce the Concurrency conceptWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: [email protected]: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.l